1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a noise suppressing circuit using a decoupling capacitor.
2. Description of the Related Art
A capacitor of a large capacitance is generally connected to a power supply to reduce a power supply noise. However, in a report of the magazine of Nikkei Electronics (2005.7.18 pp. 115-127), it is described that “different from technical common sense, when the capacitance of a decoupling capacitor is increased, power supply noise increases”. Like this case, there is a possibility that the noise can be suppressed, by increasing or decreasing the capacitance of the decoupling capacitor. Also, in a JST failure knowledge database: case name “a large power supply noise is generated in a power supply layer due to resonance of a print circuit board” (http://shippai.jst.go.jp/fkd/Detail?fn=0&id=CA0000078&), it is described that “it is generally difficult to estimate the frequency of the board”. In other words, it is desirable to dynamically control a decoupling capacitance in accordance with each frequency.
In conjunction with the above description, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-P2002-246548A). This conventional semiconductor device has a bypass capacitor of a MOS structure which has a gate electrode and which is formed on a diffusion region of a conductive type through a capacitive insulating film below a power supply wiring area, and a substrate contact which is formed below a ground wiring area to fix a substrate voltage. A bypass capacitor has a contact connected with a power supply wiring line in the gate electrode surface, and the diffusion region of the conductive type and a diffusion region of the substrate contact are connected. Thus, in this conventional semiconductor device, the number of through-holes for decoupling capacitances to be connected is changed on layout. Also, it is possible to select a bypass capacitor to be used in accordance with an operation frequency.
Also, a semiconductor integrated circuit design supporting apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2004-086881A). In this conventional LSI design technique, a gate level logic circuit data, a standard cell library data and a package data of a circuit block of an LSI chip are provided, and a noise analysis process of the LSI chip is executed by using these data. It the noise generation quantity is within a predetermined range, the process is ended. When the noise generation quantity exceeds a predetermined range, one of logic gates in the circuit block is selected, and a bypass capacitor is added to the selected logic gate.
However, in the above conventional techniques, since a layout is fixed, the capacitance cannot be changed dynamically.